以下の発表があります
The Workshop on Emerging Test Technologies (ETT) embedded in the 34th Asian Test Symposium (ATS2025)
Dec19(Fri)
LLM–Driven Testability Analysis for Gate-Level Circuits
*Akitaka Ide, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi (Ehime University, Japan)
A Boundary Scan Design with Interconnect Delay Testing and Region-based Repair for TSVs
*Haruhisa Tsuruoka, Hiroyuki Yotsuyanagi(Tokushima University, Japan), Masaki Hashizume(The Open University of Japan, Japan), Senling Wang, Yoshinobu Higami, Hiroshi Kai, Hiroshi Takahashi(Ehime University, Japan), Tianming Ni(Anhui Polytechnic University, China) and Xiaoqing Wen(Kyushu Institute of Technology, Japan)
THE 34TH IEEE ASIAN TEST SYMPOSIUM (ATS2025)
Dec17(Wed)
Software-Defined Secure Island for Testing Chiplet Systems
*Hisashi Okamoto (Ehime University), Senling Wang (Dept. of Computer Science, Faculty of Engineering, Ehime University), Hiroshi Kai, Hiroshi Takahashi, Yoshinobu Higami (Ehime University), Hiroyuki Yotsuyanagi (Tokushima University), Tianming Ni (Anhui Polytechnic University), Tai Song (Anhui University), Xiaoqing Wen (Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology)